This invention relates to semiconductor memory devices. More particularly, this invention relates to a byte-wide semiconductor memory device having redundant columns which are mappable to input and output buffers at any one of a plurality of bit positions.
Semiconductor memory devices are often provided with redundant columns to improve manufacturing yields. The redundant columns can be programmed to replace columns having defective cells thus permitting the use of a memory device which would otherwise have to be discarded. For byte-wide semiconductor memory devices, that is devices which can input or output plural bits of data simultaneously, it is desirable that redundant columns be capable of replacing defective columns at any bit position.
One method of implementing column redundancy in a byte-wide memory device is to add a single redundant column to each bit position. In such a scheme, each redundant column can replace only a single defective column in the plurality of columns associated with that particular bit position. This technique consumes a great deal of space and is inefficient since it is highly unlikely that a defective column will be associated with each bit position. In addition, this technique is incapable of repairing memory devices having more than one defective column associated with a single bit position.
Another technique for providing column redundancy in a byte-wide memory device is described in U.S. Pat. No. 4,601,019 to Shaw et al. According to the technique described in that patent, each redundant column can be substituted for any defective column in half of an array regardless of the bit position at which the defective column is located. A separate redundancy select circuit is connected to each redundant column and stores address information corresponding to a single defective column. When a match occurs between an externally received column address and a defective column address stored in one of the redundancy select circuits, the redundant column connected to that redundancy select circuit is substituted for the defective column. Although more efficient than the previously described technique, the fact that each redundant column has a separate redundancy select circuit requires more space and a layout which is more complex than desirable.
Accordingly a need exists for a byte-wide memory device having redundant columns and associated control circuitry which require a minimum of space in which the redundant columns are capable of being mapped to any input and output buffer in order to replace defective columns at any bit position.